This is a rewritten from scratch cpu. 5 byte + 1 bit fixed width, byte addressable.
Roughly 65% as dense as the previous version.
Built for vectorisation with pointer hook and index rather than only index.
32 vector with larger vector untested and large vector would possibly make more per area heat than 32 unless using ddr6 technique.
In the latter case it can up to 128 vector at same clock.
Note that full performance only possible with HBM or similar memory.
I have been advised against trying to do all of: binutils gcc llvm kernel and the actual verilog so I might be unable to complete that without external help or some investment.
Note: 125 ghz is for depletion mode dynamic logic with full body channel aka “Bulgarian” whole conductor.