Heptane Central Processor Unit

The heptane computer processor is a project to create a very fast computer processor in verilog harware description language,
which will execute 9 instructions per clock cycle and will run at above 3GHz if implemented on a modern chip process.
It will be designed with ease of translation to x86/x64, arm and risc-V arhitectures, and have about 80% native performance software translator for it.

It will be available for licensing once it's ready.
Check out more detailed description here:

The heptane processor will now allow derrivative works.
Apache 2.0 License
Floating point unit completed.
ISA specification
The source code of the CPU is now on Git Hub, although not yet finished.

As of sep 2021 the Heptane CPU is in the process of testing a whole core module by creating a random program and then running it and comparing the results (fuzzing).
The source code is available on the gorand2/heptane_cpu github.com repository
The random program testing is paused right now; You can get included in the NOTICE file as having a right to manufacture the core on the patreon membership.
Please bear in mind that this core is work in progress.
The count of registers has been reduced from 32 to 20 and there is now 2 way SMT.
The code and data caches are now each 128 KB.
There is a linear search instruction for integer simd, which is new.
Support for "texture fetch" memory, where each lpddr5 channel can be fetched from separately, rather than a whole cache line,
with short term caching of only 4 entries per core and invalidation of the texture fetch cache on
a pipeline exception stall.
It can also be used for e.g. associative arrays so that multiple cores can fetch more entries from lpddr5 when they all do it
Also there are new conditional ALU operations, but, unlike normal ALU, those have two data operands -source and target.
This is to avoid having to use a third data port for the old value of the register.