Heptane Processor

The heptane computer processor is a processor (CPU) with out-of-order
execution which pack it's program instructions (risc like) into 256-bit bundles.
Variable length encoding is used within the bundle.

The cpu has 6 alu, 3 load, 2 store units and 2 branch units
The fpu excludes 256 bit instructions and FMA instructions.
The fpu has rich "horizontal" operations

The architecture is immune to memory based speculative execution threats.
This is achieved using in-pointer 7-bit exponentiated lower and upper bound,
5 bit exponent, and an "on low bound" bit. The "on low" bit is used when the
high bound is less that the low bound. If 1, it allows one carry past top bit,
If 0, it allows one borrow past the top bit. The count of address bits is 44.
Otherwise, no carry or borrow past top bit is allowed.
Invalid address can't be accessed but can be stored in a pointer.
Note that the current implementation only checks if the starting address is in range
and so can go beyound it by up to 16 bytes.
A 65-th bit per 64 bit datum is used to indicate a pointer, so pointers can't be
loaded from a file or a network socket. Out-of-bound accesses do not initiate a
caheline or tlb insert.