About Author - Goran Dakov
I am 35 year old (in 2018).
I have learned computer programming and electronics harware design
language on my own. I have implemented a scalar risc processor in
verilog, and an assembler for it in C. I haven't made attempts to
commercialise it. It ran on a FPGA (programmable chip) and flashed some
leds. It had code cache and data cache. I coded this first processor
without any previous hardware design experience, yet it worked and has
some features better than for example open risc. i.e. single cycle
memory load from L1(as oposed to 2 in open risc), dynamic branch
prediction(none in open risc), 4-way cache (as oposed to direct
mapped). However, it didn't feature memory protection and no interrupts
since I stopped development. The reason for this is that I developed it for
the purposes of learning and I learned enough. After that, I started
working on a processor with out-of-order execution, initially 6-issue,
which I gradually developed untill it ran some loops with working
dynamic branch prediction and out-of-order execution. Then I decided to
increase the issue width to 9.
Apart from that, I have done some minor coding in c/c++ and pascal.
I have recently completed Machine Learning course on the coursera web-site.