Heptane Computer Processor


The heptane computer processor is a project to create a very fast computer processor in verilog harware description language, which will execute 9 instructions per clock cycle (as oposed to 4 by famous big company) and will run at above 2GHz if implemented on a modern chip process. It will be designed with ease of translation to x86/x64 arhitecture, and have about 80% native performance software translator for it. It will target the x86/x84 market via translation and also will feature native mode operating systerms. 
In practice, it could be used for:
High performance x86_64 tablet (single core).
High performance x86_64 laptop (dual core).
Desktop x86_64(quad/six core).
Servers and cloud (native and x86_64).



It will be available for licensing once it's ready.
Check out more detailed description here:
ABOUT PROCESSOR

Before starting the heptane project, I had written another, scalar risc processor, which i'm releasing as open source.
OTHER PROJECT

The CPU will have a version of the firmware and dynamic translator released as Open Source. There will also be a proprietary version.

ABOUT AUTHOR


Kickstarter Campaign (failed):
KICKSTARTER

GCC porting has started!
GAS assembler already assembles some instructions. As of may 2017, the Heptane CPU can execute loads,ALU operations and branches. This functionality has been tested on an infinite loop of a loop that sums integers from memory. After warmup of the branch predictor, the CPU sustained 7.5 out of 9 IPC. This is mainly due to there being one branch misprediction per inner loop. After the misprediction, it did execute at 9 IPC.
As of november 2017, the Heptane CPU can in addition execute stores that don't hit the disambiguiator or load-store forwarding.
As of february 2017, the Heptane CPU can in addition execute simple load-store forwarding that is a full match (address and size).
As of July 2018, the Heptane CPU can do more advanced store-to-load forwarding. Also, integer SIMD is working.
As of september 2018, the work on implementing the floating point units has started. FPU add and multiply main cases are ready, division is almost ready, sqrt is work in progress. The count and width of floating point units I will keep secret for now.